Transactions on Machine Intelligence 2821-1693 1 1 2018 03 01 On-Line Reusing-Based Scheduling Algorithm for 2-Dimensional Tasks in Reconfigurable Hardware 39 48 159723 10.47176/TMI.2018.39 EN A. Parisay Department of Electrical Engineering, University of Science and Technology (IUST), Tehran, Iran H. Shahriar Shahhoseini Department of Electrical Engineering, University of Science and Technology (IUST), Tehran, Iran S. M. Mohtavipour Department of Electrical Engineering, University of Science and Technology (IUST), Tehran, Iran Journal Article 2018 01 19 Reducing reconfiguration overhead is critical to improving the runtime performance of dynamically reconfigurable Field-Programmable Gate Arrays (FPGAs). In this paper, we introduce a novel task-reuse strategy tailored for two-dimensional FPGA hardware layouts. The key idea is to identify and exploit repetitive computations by reusing already‐configured hardware modules rather than incurring costly bitstream reloads. First, incoming tasks are classified into two categories significant (high‐impact or frequently appearing) and non-significant based on metrics such as execution frequency, resource intensity, and temporal locality. Each category is assigned to its own hardware partition. Within the significant partition, when a new significant task arrives, the system either replaces an existing module whose future utility is low or, if sufficient empty regions exist in the non-significant partition, temporarily maps the task there. If neither option is feasible, the partition boundary is extended to accommodate the new module, up to predefined physical limits. We evaluated our approach on a suite of benchmark applications exhibiting high task repetition. Compared to leading dynamic‐reconfiguration algorithms, our method reduced overall makespan by 20.3% on average. Moreover, the task-placement decision algorithm operates in polynomial time, achieving placement decisions over three times faster than competing strategies. These results demonstrate that intelligent partitioning combined with selective reuse and partition‐border extension can substantially lower reconfiguration overhead and accelerate FPGA‐based computation pipelines. https://www.tmachineintelligence.ir/article_159723_9e40291e8def2a62d9ccfc7db4c5ad58.pdf