Transactions on Machine Intelligence

Transactions on Machine Intelligence

A Low-Cost 16×16 and 32×32 DCT Architectures for HEVC Application Using Configurable Constant Multipliers

Document Type : Original Article

Authors
R. Younesi 1
S. M. J. Rastegar Fatemi 1
M. Rastegarpour 2
1 Department of Electrical Engineering, Saveh Branch, Islamic Azad University, Saveh, Iran
2 Department of Computer Engineering, Saveh Branch, Islamic Azad University, Saveh, Iran
10.47176/TMI.2019.99
Abstract
This paper introduces a novel area-efficient Discrete Cosine Transform (DCT) architecture designed for the High Efficiency Video Coding (HEVC) standard, a recently introduced international video compression standard. The DCT architecture is capable of performing 16 and 32-point DCT computations, which are essential for HEVC applications. Given the high complexity associated with larger transform sizes in the HEVC standard, the focus of this paper is primarily on developing efficient solutions for these larger point DCT transform sizes. The key innovation lies in leveraging commonality in constant multiplications through the use of configurable constant multipliers, aiming to reduce the area cost and hardware utilization. Consequently, the proposed architecture exhibits a significant reduction in the number of adder and shift blocks compared to existing architectures. Experimental results, conducted for the 90-nm technology node, indicate a remarkable 42% reduction in area consumption compared to other architectures. Furthermore, the proposed DCT architecture is demonstrated to support real-time 4K video resolution.
Keywords
DCT
HEVC
Multiple Constant Multiplication
VLSI
Low-Cost
[1]    Shabani A, Timarchi S, Mahdavi H. Power and area efficient CORDIC-Based DCT using direct realization of decomposed matrix. Microelectronics Journal 2019;91:11–21. https://doi.org/10.1016/j.mejo.2019.07.008.
[2]    Shabani A, Timarchi S. Low-power DCT-based compressor for wireless capsule endoscopy. Signal Processing: Image Communication 2017;59:83–95. https://doi.org/10.1016/j.image.2017.03.003.
[3]    Park JS, Nam WJ, Han SM, Lee S. 2-D large inverse transform (16x16, 32×32) for HEVC (High Efficiency Video Coding). Journal of Semiconductor Technology and Science 2012;12:203–11. https://doi.org/10.5573/JSTS.2012.12.2.203.
[4]    Budagavi M, Sze V. Unified forward+inverse transform architecture for HEVC. In: Proceedings - International Conference on Image Processing, ICIP; 2012. p. 209–12. https://doi.org/10.1109/ICIP.2012.6466832.
[5]    Jridi M, Meher PK. Scalable approximate DCT architectures for efficient HEVC-compliant video coding. IEEE Transactions on Circuits and Systems for Video Technology 2017;27:1815–25. https://doi.org/10.1109/TCSVT.2016.2556578.
[6]    Voronenko Y, Püschel M. Multiplierless multiple constant multiplication. ACM Transactions on Algorithms 2007;3:11--es. https://doi.org/10.1145/1240233.1240234.
[7]    Budagavi M, Fuldseth A, Bjontegaard G, Sze V, Sadafale M. Core transform design in the high efficiency video coding (HEVC) Standard. IEEE Journal on Selected Topics in Signal Processing 2013;7:1029–41. https://doi.org/10.1109/JSTSP.2013.2270429.
[8]    Hassanzadeh A, Shabani A. Low Power Parallel Prefix Adder Design Using Two Phase Adiabatic Logic. Journal of Electrical and Electronic Engineering 2015;3:181. https://doi.org/10.11648/j.jeee.20150306.11.
[9]    Tummeltshammer P, Hoe JC, Puschel M. Time-multiplexed multiple-constant multiplication. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 2007;26:1551–63.
[10]    Bossen F, Sühring K. Joint Collaborative Team on Video Coding (JCT-VC) of ITU-T SG16 WP3 and ISO/IEC JTC1/SC29/WG11 2015:1–30. Available: https://hevc.hhi.fraunhofer.de/svn/svn HEVCSoftware/tags/HM-8.0/.
[11]    Fong CK, Han Q, Cham WK. Recursive Integer Cosine Transform for HEVC and Future Video Coding Standards. IEEE Transactions on Circuits and Systems for Video Technology 2017;27:326–36. https://doi.org/10.1109/TCSVT.2015.2513664.
[12]    Ahmed A, Shahid MU, Rehman AU. N point DCT VLSI architecture for emerging HEVC standard. VLSI Design 2012;2012. https://doi.org/10.1155/2012/752024.
[13]    Masera M, Martina M, Masera G. Adaptive Approximated DCT Architectures for HEVC. IEEE Transactions on Circuits and Systems for Video Technology 2017;27:2714–25. https://doi.org/10.1109/TCSVT.2016.2595320.
[14]    Darji AD, Makwana RP. High-performance multiplierless DCT architecture for HEVC. In: 19th International Symposium on VLSI Design and Test, VDAT; 2015. p. 1–5. https://doi.org/10.1109/ISVDAT.2015.7208051.
[15]    Park SY, Meher PK. Flexible integer DCT architectures for HEVC. In: Proceedings - IEEE International Symposium on Circuits and Systems; 2013. p. 1376–9. https://doi.org/10.1109/ISCAS.2013.6572111.
Transactions on Machine Intelligence
Volume 2, Issue 2
Spring 2019
Pages 99-107

  • Receive Date 02 February 2019
  • Revise Date 06 May 2019
  • Accept Date 19 June 2019